System Verilog

A HDL that is similar in syntax to C. It is a superset of Verilog with:

• Improved data types
• OOP
• Assertions and coverage for function verification

Simulating .sv File

1. Write .sv file
2. With Verilator installed:

verilator --binary -j 0 -Wall hello.sv

Concepts

Fundamental

• Verilog Module
• System Verilog Datatypes
• System Verilog Enum
• System Verilog Array
• System Verilog Dynamic Array
• System Verilog Associative Array
• System Verilog Queue

Processes

• Verilog Delay
• System Verilog Fork
• System Verilog Join

Boilerplate

module my_module;
	initial
		int array[];
		array = `{5,10,15,20,25};
		foreach (array[i])
		$display("hello");
		array.delete();
endmodule