Notes
- Contact with: kareem.ibrahim@mail.utoronto.ca
- Can miss one quiz
- Can miss one lab
- Must get at least 35% on the final
- Bi-weekly labs checked at tutorials (You have two weeks to work on it)
- Tutorials are given to us
- After submission, TA will interview you, and you must be able to explain your solution
Concepts
Week 1
Week 2
- Logisim Evolution
- Karnaugh Map
- Seven Segment Display
- Logic Unit
- ALU
- Flip-Flop
- Finite State Machine
- Processor
- MIPS Assembly
- Minterm
- Maxterm
Week 3
- MUX
- DEMUX
- Encoder
- Decoder
- Half Adder
- Full Adder
- Ripple Carry Adder
- 2’s Complement
- Subtractor
- Comparator
Week 4
- Waveform
- Gate Delay
- Feedback
- Circuit State
- Latches
- Unstable State
- Race Condition
- Clock Signal
- Flip-Flop