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Text Elements
Instruction comes from EDB
Simple Pipeline Example
Fetch
Decode
Execute
Write
Get data from EDB
Figure out what command needs to be executed
Perform the operation
Write the data to a
Stalling Task
Task5
Task6
Task7
Task8
Task9
Task10
Task11
Task12
Task13
Fetch
Decode
Execute
Fetch
Decode
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Register
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Memory Address
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Arithmetic
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Read from Memory
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Interrupt
MOV A1, 0x3
ADD A1, A2
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for the sake of argument, we have an initial operation that will take multiple clock cycles
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The second operation requires the first operation be completed
Operation 1:
Operation 2:
Cycle 1
Cycle 2
Write
Cycle 3
Cycle 20
Execute
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several subsequent tasks
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This execute is waiting for the previous operation to finish
Fetch
Decode
Execute
Fetch
Decode
Execute
MOV A1, 0x3
ADD A1, A2
Operation 1:
Operation 2:
Cycle 1
Cycle 2
Cycle 3
Cycle 4
More tasks
- waitingâŠ
res
*Temporary transistor stores result
- A1 is taken from transistor
CPU
RAM
operation
SRAM 512KB
operation 1
operation 2
operation 3
SRAM is quicker and located closer to the CPU. It acts as the cache.
CPU
MCC
SRAM
RAM
Backside Bus
Frontside Bus